XCV300-5BG352I

Product Summary

The XCV300-5BG352I belongs to the Virtex FPGA family, which delivers high-performance, high-capacity programmable logic solutions. It features a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing resources. The XCV300-5BG352I is SRAM-based, and are customized by loading configuration data into internal memory cells. In some modes, the FPGA reads its own configuration data from an external PROM (master serial mode). Otherwise, the configuration data is written into the FPGA (Select- MAP, slave serial, and JTAG modes).

Parametrics

Absolute maximum ratings: (1)VCCINT, Supply voltage relative to GND: –0.5 to 3.0 V; (2)VCCO, Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF, Input Reference Voltage: –0.5 to 3.6 V; (4)VIN, Input voltage relative to GND: Using VREF: –0.5 to 3.6 V; Internal threshold: –0.5 to 5.5 V; (5)VTS, Voltage applied to 3-state output: –0.5 to 5.5 V; (6)VCC, Longest Supply Voltage Rise Time from 1V-2.375V: 50 ms; (7)TSTG, Storage temperature (ambient): –65 to +150 ℃ ; (8)TJ, Junction temperature: Plastic Packages: +125 ℃.

Features

Features: (1)Fast, high-density Field-Programmable Gate Arrays: Densities from 50k to 1M system gates; system performance up to 200 MHz; 66-MHz PCI Compliant; Hot-swappable for Compact PCI; (2)Multi-standard SelectIO interfaces: 16 high-performance interface standards; Connects directly to ZBTRAM devices; (3)Built-in clock-management circuitry: Four dedicated delay-locked loops (DLLs) for advanced clock control; Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets; (4)Hierarchical memory system: LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register; Configurable synchronous dual-ported 4k-bit RAMs; fast interfaces to external high-performance RAMs.

Diagrams